This invention relates to integrated circuits, and more particularly, to semiconductor structures such as Dynamic Random Access Memories (DRAMS) which use multiple level metallization through high aspect ratio vias through insulating layers.
The feature size for semiconductor chips has been reduced from 0.50xe2x96xa1micron in 1993 to 0.18 micron in 1999 with a projected reduction in feature size to 0.10xe2x96xa1micron in 2002. The product that is driving the decrease in feature size is the DRAM chip. This trend in feature size reduction is leading to an increase of three times more information per cm2. Different mask levels are needed for multilevel metal processes for DRAM or other similar devices. Each mask level must be aligned to the previous level to assure that all features are aligned properly one to the other. With feature sizes of  less than 0.13xe2x96xa1micron in current use for memory devices, very small misalignments can cause catastrophic results.
Most advanced circuitry relies on alignment tools (steppers) to match the alignment and overlay marks of one level to the corresponding marks on the next layer. A stepper is an alignment tool that aligns and exposes one (or a small number) of die (chip) at a time. The tool xe2x80x9cstepsxe2x80x9d to each subsequent die on the semiconductor body. Alignment and overlay marks are targets on the mask and semiconductor body used for correct alignment and overlay of a pattern on one layer to a pattern on the next layer. These marks are etched into their respective patterns and become a permanent part of the wafer. Alignment tools, typically, rely on light optics for feature sizes of 0.13 micron and larger. For products that use several conducting layers for interconnecting the device circuitry, typically, only the top conducting layer uses a relaxed feature size.
As photolithographic processes are developed to accommodate smaller line widths it becomes more difficult to fill the resulting high aspect ratio vias and trenches with a conductor. Some of the more advanced technologies are faced with the prospect of filling patterns with aspect ratios that may be as high as five. Current technologies are using the Chemical Vapor Deposition (CVD) of tungsten as the metallurgy of choice to fill the vias that connect to the device contacts. However, aluminum, when compared with tungsten, has a lower resistivity and a lower melting point, and becomes the metal of choice for the upper levels of metal on devices such as DRAMS. A heated substrate can be used to help fill high aspect ratio vias as long as the time and temperature of deposition are consistent with the thermal budget.
Previous attempts to use aluminum for high aspect ratio vias have shown that conventional aluminum processes would not fill these openings, thus there will be left behind voids which can result in reliability failures. If the voids are interconnected, contaminants can be trapped in them leading to damage of the underlying materials or to materials, which are subsequently formed on the surfaces of the conductive vias. This problem will most likely be manifested during a thermal cycle as the entrapped contaminants can be changed into gases.
Processes that use PVD or CVD for depositing a conductive material, such as aluminum, onto a hot substrate do not, necessarily, completely fill high aspect ratio vias. Also, the high substrate temperature results in the formation of a structure with very large grains. It has been demonstrated that aluminum layers deposited onto substrates heated to 400 degrees C. usually results in the formation of two or three vertical grain boundaries across the diameter of the via. The problem with very large grains is that the surface of the metallurgy becomes rough as extra atoms either pile up at a grain boundary to form a peak on the surface or diffuse away more rapidly at a grain boundary to leave a depression. The surface roughness produced by this phenomenon has a considerable impact on the alignment of masks needed to process additional layers.
Lithographic processes require that alignment marks be reflective (smooth) and provide good contrast compared to other features on the surface of the semiconductor body . Also, it is critical that the conductive material does not overlap the edges of the alignment and overlay marks. Conductor materials, which have rough surfaces and also overlap the edges of the alignment and overlay marks can result in misalignments when the automated alignment tools (steppers) are unable to successfully locate clear, sharp edges.
It is desirable to overcome these problems through the use of a process that provides relatively smooth, reflective surfaces with good contrast and the elimination of edge overlap.
The present invention is directed to a method for depositing aluminum layers onto a semiconductor body so that alignment marks are clearly visible when using automated steppers for alignment.
In a preferred embodiment the present invention is directed to a method of forming aluminum conductors through insulating layers above a semiconductor body by first forming a titanium layer over side walls and a bottom of a via. A layer of titanium nitride is then formed over the titanium. A nucleation (seed) layer of chemical vapor deposited aluminum (CVD) is then formed over the titanium nitride. A physical vapor deposited layer of aluminum is then formed over the CVD aluminum layer while heating the resulting structure at about 400 degrees C. so as to completely fill the vias and to over flow the vias and to form a blanket layer of aluminum on a top surface of the vias. The blanket layer of aluminum is then patterned and portions not covered by the pattern are removed to result in columns of aluminum. A second insulating layer is then formed around the columns of aluminum. The ends of the columns at a top of the second insulating layer lie in a relatively common plane to which steppers can relatively easily align patterns.
Viewed from a method aspect, the present invention is directed to a method of forming aluminum conductors over a semiconductor structure comprising a semiconductor body having defined therein and formed on a top surface thereof contact regions to which electrical contacts are to be made, a first plurality of electrical conductors which have first ends that contact the contact regions, which extend above the top surface of the semiconductor body and are electrically isolated from each other by portions of a first insulating layer, and which have second ends which are in an essentially common plane. The method comprises the steps of: forming a second insulating layer over the first insulating layer; forming vias through the second insulating layer with each via being in communication with one of the first plurality of electrical conductors; covering sidewalls and a bottom of each of the vias through the second insulating layer with a conductive layer; covering each conductive layer with a nucleation layer of chemical vapor deposited aluminum; overfilling each of the vias through the second insulating layer with physical vapor deposited aluminum deposited at a temperature below the melting point of aluminum but close enough such that aluminum fills the vias through the second insulating layer and forms a blanket layer of aluminum above a top surface of the second insulating layer; applying a patterning layer over the blanket layer of aluminum which leaves surface portions thereof uncovered; removing aluminum in the areas not covered by the patterning layer to leave columns of aluminum which extend into the vias of the second insulating layer; and forming a third insulating layer around the columns of aluminum.
Viewed from an apparatus aspect, the present invention is directed to a semiconductor structure comprising a semiconductor body, a first plurality of electrical conductors, first, second and third insulating layers, and a plurality of physical vapor deposited aluminum conductors. The semiconductor body has defined therein and formed on a top surface thereof contact regions to which electrical contacts are to be made. The first plurality of electrical conductors have first ends that contact the contact regions and extend above the top surface of the semiconductor body and are electrical isolated from each other by portions of a first insulating layer. They have second ends which are in an essentially common plane. The second insulating layer overlying the first insulating layer and defining a plurality of vias therethrough. A bottom portion of each of the vias through the first insulating layer-is aligned to a second end of one of the first conductors. Sidewalls and the bottom portion of each via through the second insulating layer are lined with a conductive layer covered by a chemical vapor deposited nucleation layer of aluminum. The third insulating layer overlying the second insulating layer and defining a plurality of vias therethrough with each via being aligned to a bottom portion of a via through the second insulating layer. The plurality of physical vapor deposited aluminum conductors being deposited at a temperature below the melting point of aluminum but close enough such that the deposited aluminum flows, each of the physical vapor deposited aluminum conductors contacting the chemical vapor deposited aluminum layer at first ends thereof and filling the vias through the second insulating layer and having a second end thereof that extending through vias of the third insulating layer, the top surfaces of the second ends of the physical vapor deposited aluminum conductors lie in a relatively common plane.